Silicon Labs /Series1 /EFR32MG13P /EFR32MG13P732F512GM32 /VDAC0 /CTRL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DIFF)DIFF 0 (SINEMODE)SINEMODE 0 (OUTENPRS)OUTENPRS 0 (CH0PRESCRST)CH0PRESCRST 0 (1V25LN)REFSEL 0 (NODIVISION)PRESC0 (8CYCLES)REFRESHPERIOD 0 (WARMUPMODE)WARMUPMODE 0 (DACCLKMODE)DACCLKMODE

REFRESHPERIOD=8CYCLES, PRESC=NODIVISION, REFSEL=1V25LN

Description

Control Register

Fields

DIFF

Differential Mode

SINEMODE

Sine Mode

OUTENPRS

PRS Controlled Output Enable

CH0PRESCRST

Channel 0 Start Reset Prescaler

REFSEL

Reference Selection

0 (1V25LN): Internal low noise 1.25 V bandgap reference

1 (2V5LN): Internal low noise 2.5 V bandgap reference

2 (1V25): Internal 1.25 V bandgap reference

3 (2V5): Internal 2.5 V bandgap reference

4 (VDD): AVDD reference

6 (EXT): External pin reference

PRESC

Prescaler Setting for DAC Clock

0 (NODIVISION): undefined

REFRESHPERIOD

Refresh Period

0 (8CYCLES): All channels with enabled refresh are refreshed every 8 DAC_CLK cycles

1 (16CYCLES): All channels with enabled refresh are refreshed every 16 DAC_CLK cycles

2 (32CYCLES): All channels with enabled refresh are refreshed every 32 DAC_CLK cycles

3 (64CYCLES): All channels with enabled refresh are refreshed every 64 DAC_CLK cycles

WARMUPMODE

Warm-up Mode

DACCLKMODE

Clock Mode

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